In a conventional network system, an interconnection of data communications devices transmits message traffic between users. Such conventional data communications devices perform switching of message traffic to transport the message traffic from a source node to a destination node. Conventional message traffic typically includes a series of packets, each containing a source and destination address, corresponding to the source and destination nodes, respectively. Switching engines in conventional data communications devices read the address information in the packets, and switch the packets to an outgoing line corresponding to the destination node.
In such a conventional network, a message packet is transported via multiple data communications devices between the source node and the destination node, in a series of “hops” along the interconnections. In such conventional data communications devices, the switching engines typically transport many packets corresponding to many different source and destination nodes. Accordingly, fast switching of the message packets is desirable to maintain message packet throughput, while minimizing the number of switching engines which the network employs for transporting the message traffic through the network.
Accordingly, conventional switching engines typically employ high-speed memory and processing control circuits between a plurality of ingress and egress ports. The physical network interconnections connect to the ingress and egress ports, each of which in turn, connect to other data communications devices having conventional switching engines, or to the end-user nodes themselves. Therefore, the high-speed memory and processing control circuits in conventional switching engines switch the packets in the ingress message traffic onto the egress ports at a rate such that the switching engines avoid a bottleneck of message traffic.
Accordingly, such conventional switching engines employ a scheduler to facilitate message throughput through the data communications device. Such a scheduler manipulates the high-speed memory and processing control circuits via a predetermined algorithm that quickly reads and interprets the address and other information in the packets. The scheduler then makes determinations, using the predetermined algorithm, concerning which message packets to transmit next on the egress ports. In this manner, a conventional scheduler prioritizes message traffic according to a variety of factors, such as packet address information, observable by such a conventional predetermined algorithm, in order to determine which packets to transmit and on which egress ports. Since the throughput through the data communications device depends largely on the conventional predetermined algorithm, the predetermined algorithm specifies a sequence of instructions operable to perform the switching operations such that many throughput events per second, corresponding to messages, are achievable.
However, such conventional high-speed memory and processing circuits in the scheduler are expensive, and increase the cost of the resulting data communications device. Therefore, excessive or unrestrained usage of such high-speed memory and processing circuits is undesirable in a conventional scheduler. Accordingly, a design process for a conventional data communications device includes selecting high-speed memory and processing circuits for the conventional scheduler therein, while achieving a balance between the cost of such high-speed memory and processing circuits and the throughput capacity of the resulting data communications device. Ideally, such a balance avoids bottlenecks in the network context into which the user employs the data communications device, while achieving an acceptable cost/performance factor for the user.